The biggest gains surround the L1 cache, branch predictor, execution window, and core processing throughput.
The slide also lists additional data prefetch improvements along with ISA and Security enhancements but doesn’t go into any specific details.
The new change marks the first time since Zen 2 that AMD has bothered to increase the core count of its CCXs, which means that we could see a 32-core “Ryzen 9 8950X” in the future.
It’s worth mentioning that these slides are strictly targeted toward AMD’s enterprise server chips (EYPC) and aren’t focused on its mainstream consumer desktop CPUs.
The leaked slides also show additional projections regarding AMD’s Zen 6 architecture.
The slide shows that Zen 6 will have an estimated IPC target of at least 10% at the very minimum, FP16 for AI/machine learning, and a new memory profiler.
The original article contains 534 words, the summary contains 137 words. Saved 74%. I’m a bot and I’m open source!
This is the best summary I could come up with:
The biggest gains surround the L1 cache, branch predictor, execution window, and core processing throughput.
The slide also lists additional data prefetch improvements along with ISA and Security enhancements but doesn’t go into any specific details.
The new change marks the first time since Zen 2 that AMD has bothered to increase the core count of its CCXs, which means that we could see a 32-core “Ryzen 9 8950X” in the future.
It’s worth mentioning that these slides are strictly targeted toward AMD’s enterprise server chips (EYPC) and aren’t focused on its mainstream consumer desktop CPUs.
The leaked slides also show additional projections regarding AMD’s Zen 6 architecture.
The slide shows that Zen 6 will have an estimated IPC target of at least 10% at the very minimum, FP16 for AI/machine learning, and a new memory profiler.
The original article contains 534 words, the summary contains 137 words. Saved 74%. I’m a bot and I’m open source!